发明名称 Data processing method and apparatus
摘要 <p>A data processing apparatus and a data processing method for implementing data-tuning rapidly, in which when CPU is operating based on PROM data, it permits operation to implement while referring to data which is rewritten to RAM without stop of the operation. There is provided a CPU core for performing program operation for the purpose of implementing of data processing, a PROM for storing data which is referred at the time of data processing, a register for memorizing a data-stored-address, and a comparator for comparing an address. The comparator is brought into effective when the data-stored-address is outputted while rewriting the RAM during executing the CPU core, comparing the data-stored-address memorized within the register with an address outputted from the CPU core, bringing the RAM selection signal into active when both correspond with each other, while bringing the PROM selection signal into inactive, after receiving thereof the CPU core refers to the data stored within the RAM instead of the data stored within the non-volatile memory, thereby a data-tuning is capable of being realized without stop of operation. &lt;IMAGE&gt;</p>
申请公布号 EP0817013(A2) 申请公布日期 1998.01.07
申请号 EP19970110521 申请日期 1997.06.26
申请人 NEC ELECTRONICS CORPORATION 发明人 IENAGA, TAKASHI
分类号 F02D45/00;G05B19/05;G06F9/312;G06F12/06;(IPC1-7):G06F9/445;G06F11/20;G06F9/26 主分类号 F02D45/00
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