| 摘要 |
A plan-view sample of an integrated circuit is prepared for transmission electron microscopy by marking a faulty circuit element, lapping the upper surface of the sample to a mirror finish, lapping the lower surface to reduce the thickness of the entire sample, and further processing the lower surface by lapping or dimpling, combined with ion milling as necessary, to thin the sample in the vicinity of the fault. A sample prepared in this way affords a wide view, and can be tilted at large angles. A known thickness of a particular type of layer in the sample can be left by holding the sample at a predetermined angle while the sample is lapped. |
