| 摘要 |
A hybrid Harvard/Von Neumann data processing system utilizes a Harvard architecture processor with a combined data/instruction memory. A dual-port random-access instruction buffer between memory and the processor provides much of the performance enhancement of an instruction cache when used with a RISC instruction set, but at a much lower cost. The resulting system serves as an entry-level computer system of a series of compatible computers, led at the high end by a Harvard processor with full data and instruction caches.
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