| 摘要 |
Method and apparatus for more efficiently using the undefined logic state and mixed multiple state abstractions is described. The method involves dividing gates into two groups: those that require an 8-state table (either because their inputs are sensitive to 8-state values or their output produces an 8-state value), and those that require only 4-state values (their inputs are insensitive to 8-state values and the output produces only 4-state values). The key to obtaining the advantages of the invention is the choice of the 4-state values. Previously, the 4-state values have been 0, 1, X, and Z. By the invented method and apparatus, the 4-state values are defined instead to be 0S, 1S, XS, and U. In the Multi-value Logic 9-state model (MVL-9), U is defined to be the uninitialized state, and thus it is a state that all instances need to process on their inputs and to produce as an output. The Z (or high-impedance) state, on the other hand, is used only for certain specialized gates-typically tri-state buffers-and so the Z state is used only rarely in digital logic simulation. By shifting the definition of the 4-state abstraction from (0, 1, X, Z) to (0S, 1S, XS, U), almost all gates may be included in the 4-state category, thus allowing higher pin counts for the average digital logic simulation. The invented method and apparatus nevertheless permits the interconnection of 4-state values and 8-state values, while placing the significant overhead of the latter on the rare use thereof. Preferably, both 4-state and 8-state directives-instructions to a downstream gate that tells the gate how to attain a new state-are provided by the invented method and apparatus, and the gate receiving such plural directives effectively decides whether to use the 4-state abstraction or the more expensive 8-state abstraction.
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