| 摘要 |
A method of extracting parasitic capacitance values from the physical design of an integrated circuit, and more particularly, to a method of extracting lateral coupling and fringing capacitance values from the physical design of an integrated circuit, wherein the integrated circuit comprises multiple layers of conductors, each conductor having one or more lateral edges. The method comprises the steps of identifying each conductor's one or more lateral edges; fragmenting the lateral edges of each conductor into edge fragments based on a number of conductors present in layers above and/or below a given lateral edge; identifying the edge fragments which are laterally adjacent to each edge fragment; computing one or more relationships between an edge fragment and each of its laterally adjacent edge fragments; retrieving parasitic capacitance data for each edge fragment; and using the retrieved parasitic capacitance data to compute one or more parasitic capacitance values for each edge fragment. Disadvantages of prior methods are overcome in that extracted lateral coupling capacitances are based on the presence of conductors running above and/or below a given lateral conductor edge, and fringing capacitances are based on the spacing between a given lateral conductor edge and a laterally adjacent conductor edge.
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