发明名称 Low noise 3V/5V CMOS bias circuit
摘要 The present invention concerns a circuit for implementing a low noise bias circuit that operates at 3 volts, 5 volts or any desired power supply voltage while avoiding production reconfiguration or post-production configuration. The present invention is implemented by using a current source designed to provide a constant current under differing conditions (e.g., such as a variation in temperature, a variation in power supply, or conditions encountered in a fast transistor process). The present circuit provides a means to adapt to varying conditions. The present circuit generally provides two bias signals that are typically used in a pre-driver circuit implementing NMOS and PMOS transistors.
申请公布号 US5705921(A) 申请公布日期 1998.01.06
申请号 US19960635022 申请日期 1996.04.19
申请人 CYPRESS SEMICONDUCTOR CORPORATION 发明人 XU, PING
分类号 G05F3/20;(IPC1-7):G05F3/16;H02J1/04 主分类号 G05F3/20
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