| 摘要 |
The display data read out circuit of this invention includes a CPU, data and address buses, a display data address circuit, and an address switching circuit. In a case where a refresh signal from the CPU is in an enable state, the address switching circuit outputs a display data address, obtained from the display data address circuit, into an external memory through the address bus. On the other hand, when the refresh signal is not in the enable state, the address switching circuit outputs an address from the CPU into the external memory through the address bus. Thus, the circuit of this invention transfers display data into the external display using the refresh period of the CPU. This improves the throughput of this CPU.
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