发明名称 Method of manufacturing a semiconductor device with flattened multi-layer wirings
摘要 A wiring layer formed on a field insulating film covering the surface of a semiconductor substrate is covered with an interlayer film. The interlayer film is covered with a flat film such as spin-on-glass formed by spin coating. The flat film has, for example, a laminated structure of an organic SOG film and an inorganic SOG film. The inorganic SOG film is suitable for obtaining a polishing speed generally equal to that of a CVD oxide film. The insulating film and the flat film are chemical-mechanical polished at a same polishing speed until the flat film is thoroughly removed, to leave a planarized insulating film.
申请公布号 US5705028(A) 申请公布日期 1998.01.06
申请号 US19960605709 申请日期 1996.02.22
申请人 YAMAHA CORPORATION 发明人 MATSUMOTO, YASUHIKO
分类号 H01L21/304;H01L21/3105;H01L21/316;H01L21/768;(IPC1-7):H01L21/304 主分类号 H01L21/304
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