摘要 |
General purpose parallel computer, latency reduction MIMD, with multiple processors, and multiple memory address spaces, wherein processors (SPU) are redundantly replicated on each memory (M) bus (C-BUS) and, formed/connected as either master-active or slave-active of the bus and to interface a suitable communication structure (A-S) for transferring among themselves the process context and the bus control, in such a way to execute in turn a unique migrant sequential process per bus (C-BUS), and wherein each processor is also directly and tightly coupled with devoted private buses (P-P) to one corresponding processor of another one bus (C-BUS) in a way to form, between distinct buses (C-BUS), biprocessor pairs (DPU) capable of allowing communication and synchronization of the parallel migrant processes. |