发明名称 |
Synchronous memory system with asynchronous internal memory operation |
摘要 |
A memory system is provided which is capable of eliminating deterioration in a processing rate due to possible signal delays between an input/output circuit and memory blocks. Complication of design is also reduced, especially when the scale and chip area of the memory system increase. A memory chip includes a plurality of memory array blocks each including an address buffer and an address counter, and operates on the basis of a local clock cycle. A control circuit is synchronous with a clock of an external device, and synchronous data-transfer circuitry includes a buffer which modulates the transfer rate of serial data which arrives from a memory array block at a local clock cycle so as to be synchronous with the clock of the control circuit. External clock signal lines are not distributed to the memory array blocks.
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申请公布号 |
US5706474(A) |
申请公布日期 |
1998.01.06 |
申请号 |
US19950455155 |
申请日期 |
1995.05.31 |
申请人 |
HITACHI, LTD.;HITACHI ULSI ENGINEERING CORPORATION |
发明人 |
TAKEUCHI, KAN;HORIGUCHI, MASASHI;AOKI, MASAKAZU;SAKATA, TAKESHI;TANAKA, HITOSHI;MATSUNO, KATSUMI |
分类号 |
G11C11/407;G06F12/00;G06F13/16;G11C7/10;G11C11/401;G11C11/409;(IPC1-7):G06F12/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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