Synchronisation circuit for redundantly transmitted message cell flows

摘要

The circuit (AS) contains only one memory (SM) and operates on check cells introduced at fixed intervals into two flows of message cells transmitted over active and substitute paths (EP,AP) and numbered in sequence. The memory brings together the two paths by means of a data switch (S1) and a path selector (S2). An evaluation unit (A) interposed between the memory and the path selector is linked to a controller (C) incorporating a counter (Z). The flows are monitored for check cells, and the one found to be in advance is delayed until similarly numbered check cells appear in both flows.