| 摘要 |
The method is used for an integrated circuit having at least one input register (E1), at least one logic circuit (LS) with a number of memory elements, a control logic circuit (SL) controlling the testing sequence and at least one output unit (AE). Memory elements which are not assigned to an input register or output unit are employed for a test chain, with at least part of the logic circuit used for association cones (AK1,..AK4) which each have a number of inputs and a single output. The inputs of the association cones are coupled to memory elements contained in the input register or the logic circuit.
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