| 摘要 |
A self-aligned planarization and isolation technique achieves smaller dimension memory cells using self-aligned isolation trenches. The process involves defining lines of buried diffusion (54, 55, 56) and first layer of polysilicon using a single mask. A protective oxide (58) is formed between the polysilicon lines (50, 51, 52, 53). Then a second mask (60) is used with non-critical alignment to select polysilicon lines (50, 52) to define self-aligned etch regions. The trenches are made using a high selectivity etching recipe which etches through polysilicon (50, 52) and the silicon substrate (10) in the selected lines faster than the protective oxide (58). Thus, a single mask defines the diffusion regions, the first layer of polysilicon, and the isolation trenches. The mask used for selecting polysilicon lines for definition of isolation structures does not need to be critically aligned, removing the alignment tolerance for formation of the isolation structures out of the layout of the array.
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