APPARATUS FOR SYMMETRICALLY REDUCING N LEAST SIGNIFICANT BITS OF AN M-BIT DIGITAL SIGNAL.

摘要

An M-bit digital signal, the MSB thereof and an integer K are added to produce a sum which is truncated by N least significant bits to provide a symmetrically rounded bit-reduced digital output signal, The MSB may be applied in true or complemented form to the adder for selecting wide or narrow rounding modes having different numbers of output zeros disposed about a point of symmetry for a given input signal change. Advantageously, undesirable DC shifts due to least significant bit (LSB) reduction in digital video, audio or similar applications are prevented.