| 摘要 |
A semiconductor memory device capable of restricting an increase of a gate capacitance of a substitution address program circuit connected to an address bus and reducing charge/discharge current of the substitution address program circuit to reduce current consumption of a chip and to restrict an increase of time from a time instance when an address signal is input to a time instance when a redundancy selection signal is output is provided. Addresses containing defects are programmed by fuses 2 and a node PRE has a potential swung between a first potential which is lower than a power source potential and higher than a reference potential VREF which is set to an intermediate potential between the power source potential and a ground potential and a second potential lower than the reference potential and higher than the ground potential. A differential amplifier 10 determines a coincidence or non-coincidence of the input address with the program address by comparing the potential of the node PRE with the reference potential and generates a redundancy determination signal RED correspondingly thereto.
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