发明名称 Serial access memory device including memory sections having different latencies
摘要 In a serial access memory device, a first memory section divided into a plurality of first segments and a second memory section divided into a plurality of second segments are provided. A first latency of the first memory section is shorter than a second latency of the second memory section. The serial accesses of segments of the first and second memory sections are simultaneously initiated. The serial access of segments of the first memory section is completed within a time period corresponding to the second latency.
申请公布号 US5703822(A) 申请公布日期 1997.12.30
申请号 US19970788077 申请日期 1997.01.22
申请人 NEC CORPORATION 发明人 IKEDA, HIROAKI
分类号 G11C11/401;G11C7/10;G11C11/407;(IPC1-7):G11C7/00 主分类号 G11C11/401
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