发明名称 |
Synchronous type semiconductor memory device which can be adapted to high frequency system clock signal |
摘要 |
In a pipeline burst EDO operation, a latency circuit 215 detects change of an internal column address strobe signal ZCASF from an active state to a non-active sate in the first cycle, and brings a signal OEMB into an active state. When a writing operation mode is specified, and an internal output enable signal ZOEF is in an active state, an output buffer control signal OEM attains an active state in response to the first activation edge of the internal column address strobe signal ZCASF after activation of the signal OEMB. Since the signal OEMB has already been in an active state in the first cycle of the signal ZCASF, a delay time for change of the signal OEM in response to activation of the signal ZCASF in the second cycle can be decreased.
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申请公布号 |
US5703829(A) |
申请公布日期 |
1997.12.30 |
申请号 |
US19960681428 |
申请日期 |
1996.07.23 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
SUZUKI, TOMIO;MORI, SHIGERU;MIYAMOTO, TAKAYUKI |
分类号 |
G11C11/401;G11C7/10;G11C7/22;G11C11/407;G11C11/409;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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