发明名称 |
Plurality of photolithographic alignment marks with shape, size and spacing based on circuit pattern features |
摘要 |
Photolithographic alignment marks (e.g., mask and measurement overlay marks) are formed of a pattern of very small marks using the design configuration and rule of a circuit pattern feature. A relatively large mark comprising a pattern of small marks modeled after the circuit pattern feature results in an etch rate within the mark area that is substantially the same as the etch rate in the circuit pattern (e.g., cell or peripheral circuit) area. This allows for simultaneous formation of circuit pattern features, and the alignment marks, in a common etching step, while avoiding underetching (shallow etch depth) due to a microloading effect. In this manner, proper formation of readily detectible marks is ensured.
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申请公布号 |
US5702567(A) |
申请公布日期 |
1997.12.30 |
申请号 |
US19950457670 |
申请日期 |
1995.06.01 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
MITSUI, TADASHI;HIEDA, KATSUHIKO |
分类号 |
H01L21/68;G03F7/20;G03F9/00;H01L21/027;H01L23/544;(IPC1-7):H01L23/544 |
主分类号 |
H01L21/68 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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