发明名称 |
Bit processing unit for performing complex logical operations within a single clock cycle |
摘要 |
A microprocessor architecture that includes an arithmetic logic unit (ALU), a bit processing unit (BPU), a register file and an instruction register is disclosed. The BPU performs complex logical operations in a single clock cycle. The ALU continues to perform the slow arithmetic operations (e.g., multiply, divide). The BPU has two special purpose registers, a zero flag and a match flag, which are used for program execution control. The BPU performs bit manipulations on data stored in and received from the register file and/or individual fields in the instruction currently being executed by the BPU.
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申请公布号 |
US5704052(A) |
申请公布日期 |
1997.12.30 |
申请号 |
US19960635541 |
申请日期 |
1996.04.22 |
申请人 |
UNISYS CORPORATION |
发明人 |
WU, GARY C.;PAWAR, CHANDRA S.;LEIBOWITZ, STEVEN H.;PULLIN, EDWARD J.;HAZZARD, MICHAEL J.;DUGGAN, JOSEPH C. |
分类号 |
G06F7/575;G06F7/76;G06F9/308;G06F9/32;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/575 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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