发明名称 FREQUENCY SYNTHESIZER
摘要 A variable divider in which a dividing number setting parameter can be set is provided in a reference oscillator. And, when a frequency setting parameter is selected to that a DDS will not output a spurious at a specified level or at a level higher than the specified level within an output band of an PLL in response to an output frequency from the PLL, both a conversion function setting parameter for a variable divider in the PLL and a dividing number setting parameter for a variable divider in the reference oscillator are adjusted so that the output frequency and the selected frequency setting parameter are satisfied.
申请公布号 CA2195277(A1) 申请公布日期 1997.12.29
申请号 CA19972195277 申请日期 1997.01.16
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 TAJIMA, KENICHI;ITOH, KENJI;NISHIMURA, SHUJI;DOI, MASAYUKI;IIDA, AKIO
分类号 H03B28/00;H03L7/18;H03L7/183;(IPC1-7):H03K3/80 主分类号 H03B28/00
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