CMOS GATE STRUCTURE AND METHOD FOR MAKING SAME

摘要

An integrated circuit fabrication method incorporating nitrogen into the polysilicon-dielectric interface in an MOS transistor. A semiconductor substrate having a P-well region (16) and an N-well region (14) is provided. Each well region includes channel regions (13) and source/drain regions (15). A dielectric layer (20), preferably a thermal oxide, is formed on an upper surface of the semiconductor substrate. The thermal oxide can be grown in a nitrogen bearing ambient, an O2 ambient, or an H2O ambient. Alternatively, the dieletric may be formed from a deposited oxide. Therafter, a layer of polysilicon (24) is formed on the dielectric layer and a plurality of 'nitrogenated' polysilicon gates (32, 34) is formed on the dielectric layer over the channel regions. In a presently preferred embodiment, nitrogen species are introduced into the polysilicon gates with an ion implantation step. The nitrogen implantation step may alternatively be performed before or after the patterning of the polysilicon layer. If implantation occurs after patterning of the polysilicon layer, nitrogen will be introduced into the source/drain regions and effect an increase in drive current without a corresposing increase in leakage current. In a presently preferred embodiment, a dose of between 5 x 1013 cm-2 and 1 x 1016 cm-2 is used for implanting the nitrogen bearing species and the species is distributed within the plurality of polysilicon gates such that the concentration of the nitrogen is greatest at approximately a midpoint within said gates. The semiconductor substrate may be subsequently annealed in an ambient maintained bewteen approximately 900° to 1100 °C preferably using a rapid thermal anneal apparatus.