| 摘要 |
PURPOSE:To avoid the pseudo synchronizing locking even to a signal transmission of a fixed pattern having a very strong correlativity by using N-set of specific frame synchronizing pulses in one frame as a pattern signal using M- frame (M is an integral number of 2 or over) as the period. CONSTITUTION:A frequency divider circuit 101 inputs a multiplex clock 10 and outputs a frequency division signal 11 being position information of a frame synchronizing pulse. A synchronizing pattern generating circuit 102 generates a synchronizing pattern signal 12 based on the signal 11 while using one frame as one period. A pulse generating circuit 103 outputs a control signal 13 taking M-frame as the period as the specific N-set of synchronizing pulse locations in one frame based on the synchronizing pattern signal 12. An EX-OR gate 104 outputs a synchronizing pattern signal 14 being the exclusive OR between the signals 12 and 13. That is, the N-set of specific frame synchronizing pulses in one frame becomes signals changing as the M-frame as the period. A multiplex circuit 105 applies multiplex to the synchronizing pattern signal 14 onto the input signal 15 based on the control of the signal 11 and outputs the result as the multiplex signal 16. |
