| 摘要 |
<p>A multi-level memory circuit for binary information, according to the invention, comprises a plurality (MTX) of memory cells, each adapted to store more than one item of binary information and comprised of at least one floating gate MOS transistor, the information stored therein corresponding to the level of the cell threshold voltage, and a write signal generating circuit (ALIM) for the cell plurality, adapted to be input a supply voltage (VCC). The generating circuit (ALIM) is adapted to generate internally at least one write voltage (VW) having a selectable or selected (SW1, ..., SW4) value from a number of discrete regulated values corresponding to the number of the discrete levels provided.</p> |
