FLASH MEMORY ADDRESS DECODER WITH NOVEL LATCH

摘要

A flash memory (10) includes a flash transistor array (12a, 12b, 12i), a wordline decoder (14), a bitline decoder (18), a sourceline decoder (22) and a read/write controller (26). The read/write controller (26) has a voltage terminal to receive an input voltage and a data terminal configured to sense a signal on a selected bitline and to generate an internal old amplifier and configured to compare the new data signal to the old data signal and to generate a comparator signal. A voltage generator is configured to selectively apply one of a read set of voltages to program a selected cell and an erase set of voltages to erase a selected cell. In a multistate embodiment, the read/write controller further includes a step counter configured to generate a plurality of step counts. The voltage generator is coupled to the step counter and configured to generate a wordline high voltage (WLHV) signal based on the step count. The WLHV signal is delivered to a selected multistate cell by the wordline decoder to read the contents of the selected multistate cell. Each step compares the old data and the new data in order to determine which memory cells to change. Advantages of the invention include increased flexibility of programming and erasing and improved memory longevity.