发明名称 |
Parallel processor system |
摘要 |
In each processing device of a parallel processor system, a processor outputs a signal when all the transmit data are transmitted to a router. A latch receives the signal from the processor to output a signal set to HIGH. To an AND gate are inputted the signal set to HIGH outputted from the latch and a signal set to HIGH which indicates that the router has no receive data received from a network. The parallel processor system performs AND operation on the outputs of the AND gates of all the processing devices, and detects that a data transmit/receive processing is completed among all the processing devices according to the results of AND operation.
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申请公布号 |
US5701509(A) |
申请公布日期 |
1997.12.23 |
申请号 |
US19970783178 |
申请日期 |
1997.01.15 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
KANEKO, KATSUYUKI |
分类号 |
G06F15/16;G06F13/40;G06F15/173;G06F15/177;G06F15/80;(IPC1-7):G06F9/28;G06F13/42 |
主分类号 |
G06F15/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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