发明名称 MULTIPLYING METHOD FOR COMPILER
摘要 PROBLEM TO BE SOLVED: To obtain an efficient sequence of arithmetic logic unit(ALU) instructions for performing integral multiplication by generating a look-up table containing an instruction sequence for performing multiplication by a compiler. SOLUTION: All ALU instruction codes which are usable on given architecture for calculating an integral multiplication result is listed first (S200). The instruction codes are classified into instruction codes having three operands and instruction codes having two operands (S210). Further, the former instruction codes are reserved as monitor instructions marking the end of the sequence of ALU instructions (S220). Then a range of three-operand instruction codes having two inputs and one output is recorded (S230). When the development of a 64-bit integer into the ALU instruction sequence is performed (S240), one usable input is added by levels. Once all possible codes are known (S260), an integer can be developed into the ALU instruction sequence.
申请公布号 JPH09330210(A) 申请公布日期 1997.12.22
申请号 JP19970047683 申请日期 1997.03.03
申请人 HEWLETT PACKARD CO (HP) 发明人 BURAIAN SARIBAN
分类号 G06F7/53;G06F1/02;G06F7/52;G06F7/523;G06F9/45 主分类号 G06F7/53
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