| 摘要 |
<p>PROBLEM TO BE SOLVED: To improve step up efficiency and reduce a circuit scale and a layout occupied area. SOLUTION: A step up block Uk, constituted by a booster transistor Pk (k=1, 2...n) connected in diode-connection connecting a back gate substrate to a drain electrode and a booster capacitor Ck connecting one of leads to the drain electrode of the Pk, is connected in series by an n-step, the other end of the Ck in an odd step is connected to an input terminal 11 of a clockϕ, the other end of the Ck in an even step is connected to an input terminal 12 of aϕinverting clock rϕ, in each half period of the clock a charge from a voltage input terminal 13 is transferred to the next step, and an output capacitor CL is charged with a boosted output voltage Vo. Here, in the Uk, input voltage subtracting threshold voltage of Pk from clock amplitude is boosted and outputted to the next step, but a back gate substrate of P1 to Pn is respectively separated to bias, so that a back gate effect can be suppressed, and a step up value of the threshold voltage can be risen.</p> |
