| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a microprocessor which enables high-speed interruption and multiplex interruption and improves the responsiveness of interruption. SOLUTION: A microprocessor 1 has an instruction decoder 6, arithmetic operation logic unit 11, register groups 7 and 9, high-speed multiplication/division unit 12 and interruption controller 8 and the instruction decoder 6 is composed of a reduced instruction set computer for decoding an instruction set under pipeline control. Further, a vector instruction table is provided and when interruption is accepted, the vector instruction table is directly fetched. Since the vector instruction table is directly fetched when interruption is accepted, interruption processing is accelerated. Since an interruption dedicated stack pointer is provided, multiplex interruption is enabled. Since the result of a long dividing instruction is stored in a dedicated register, the responsiveness of interruption is improved.</p> |
