THE MANUFACTURING METHOD FOR S-RAM DEVICE

摘要

The method for reducing leakage current, contact resistance and improving high integrity by increasing alignment margin of butting via includes steps : a) etching selected insulation layer to form the via hole; b) forming 2nd polysilicon layer for load resistance; and c) injecting 2nd conductive type 1st impurity into the 2nd polysilicon layer up to substrate with load resistance mask as ion injection wall so that the 2nd conductive type 2nd impurity region is formed between substrate of boundary region of field oxide and junction layers.