PAGE MODE FLOATING GATE MEMORY DEVICE STORING MULTIPLE BITS PER CELL

摘要

An array (10) of multi-level floating gate memory cells includes wordlines (18) connected to memory cells along a row in the array, and bit lines (12) connected to memory cells along a column in the array. A wordline voltage source (27) is included which supplies selectively wordline voltages corresponding to respective threshold voltages of the memory cells in the array. A plurality of bit latches form a page buffer (11). Bit latches are coupled to corresponding bit lines, and have a first state and a second state. The bit latches include circuits (213-216) to change the bit latches from the first state to the second state in response to signals on the corresponding bit lines that are generated in response to a wordline voltage on a selected wordline being greater than or equal to the threshold voltage of a memory cell on the corresponding bit line connected to the selected wordline. Logic (21) controls the wordline voltage source and the bit latches to apply in a sequence the wordline voltages, and to sense the state of the bit latches after applying each wordline voltage in the sequence to determine the threshold voltages of the memory cells.