| 摘要 |
<p>A collection buffering scheme for a computer system having agents (100) of a pre-emptible bus (4) and a non-pre-emptible bus (6). An agent (110) of the non-pre-emptible bus (6), having a data width capability of N bits, when receiving a grant to write to the pre-emptible bus (4), writes instead to a collection buffer (80) capable of holding a block of more than one N bit data segments. When the collection buffer (80) is filled, the collection buffer (80) writes the entire block of data segments over the pre-emptible bus (4) to a CPU (10) or memory (60) of the computer system. Preferably, the collection buffer (80) is filled when the block size is equal to the data width capability of the pre-emptible bus (4), such that a single write to the pre-emptible bus (4) utilizes the entire capacity of the pre-emptible bus (4) in a given data transaction. Further, where the system has a CPU posting buffer (55), a system lock-up prevention negotiator is provided that drains and disables the CPU posting buffer (55) during the data transaction.</p> |
