AN OPERAND CACHE FOR REDUCING LATENCY OF READ INSTRUCTIONS

摘要

A structure for, and a method of operating an operand cache to store operands retrieved from a memory. An instruction requiring an operand stored in the memory is allowed to speculatively execute in an execution unit of a processor using an operand stored in an entry (corresponding to the address of the instruction) of the operand cache. When the actual operand is later retrieved from the memory it is compared to the cached operand used for speculative execution. If the cached and actual operands are unequal then the speculatively executed instruction and all subsequent instructions are aborted and the processor resumes execution at the address of the instruction that was speculatively executed.