| 摘要 |
<p>A method is provided for forming conducting interconnects embedded in a layer of dielectric (38) such as an interlevel dielectric layer which resides over an integrated circuit structure (10). The conducting interconnects (38) and the layer of dielectric (40) may comprise, for example, metal and oxide, respectively. A CMP process which polishes both the interconnect material (i.e., the metal) and the dielectric (i.e., the oxide) at the same rate both locally and globally is employed to simultaneously polish the conducting interconnects (38) and the layer of dielectric (40). The CMP process effectively combines two CMP processing steps into one. Thus, the method of the present invention advantageously reduces the cost of manufacturing. Additionally, since both the layer of dielectric (40) and the conducting interconnects (38) are planarized in a single polishing step which polishes the interconnect material and the dielectric (e.g., metal and oxide) at rates which are essentially the same, the surface of the conducting interconnects (44) is level or co-planar with the surface of the layer of dielectric (46). The method of the present invention can be repeated to build multiple levels of conducting interconnects (38).</p> |
