| 摘要 |
<p>PURPOSE:To effectively use an address space by reducing the address space required for the addressing of targeted hardware by selecting one of plural targeted hardware with different process data length by a data length designation signal and a selection signal, and making access to it. CONSTITUTION:An instruction decoder 1 decodes an instruction INS, and the data length designation signal DL is set at a low level when the process data length held by the instruction INS is four bits, and the data length designation signal DL is set at a high level when it is eight bits. Selection control parts 3A and 3B, when the selection signal HS being inputted from an address decoder 2, check the level of the data length designation signal DL, respectively, and a control signal HC1 is outputted from the selection control part 3A when it is set at the low level, then, the targeted hardware 10A is accessed. Also, a control signal HC2 is outputted from the selection control part 3A when the data length designation signal DL is set at the high level, then, the targeted hardware 10B is accessed.</p> |
