| 摘要 |
<p>PURPOSE:To provide a clock signal distributing circuit which can be easily designed for an integrated circuit and has the small clock skew. CONSTITUTION:A clock driver 11 which distributes the clock signals is subsidiarily connected to the circuit blocks 151-155 which has the same constitution. The block 151 includes the registers 101-104 which supply the input data to the corresponding logic circuits 121-124 respectively in response to the supply of clock signals, a delay circuit 141 which delays the clock signal supplied to the block 151, and a buffer 12 which supplies the delayed clock signal to the next circuit block. The circuit 141 synchronizes with the clock signal whose phase is shifted by a natural number multiple as much as a single clock cycle in regard of the delayed variable added to the buffer 12.</p> |
