发明名称
摘要 PURPOSE:To drive a clock circuit even at the last stage of the service life of a primary cell and, at the same time, to prevent destruction of the clock circuit caused by a latch-up phenomenon by providing a plug, power source circuit, power supply circuit, power supply switching circuit, switch circuit, plug socket, and displaying section in addition to the primary cell and clock circuit. CONSTITUTION:A clock circuit 3 stores the time of a timer and outputs a signal when the time of the timer ups. A power source circuit 4 converts AC power supply from a plug into DC power supply and outputs the DC power supply and a power supply circuit 5 outputs the output voltage of the circuit 4 as a constant low-voltage. A power supply switching circuit 6 supplies power from a primary cell 2 to the circuit 3 by utilizing a small voltage drop between the emitter and collector of a transistor when the AC power supply is disconnected and inhibits the electric current flowing into the cell 2 from the circuit 5 and, at the same time, switches the power supply to the circuit 3 from the cell 2 to the circuit 5 when the AC power supply is connected. A switch circuit 7 is driven by the output of the circuit 3 and switches the AC power supply. A plug socket 8 is connected with the output side of the circuit 7 and a load is connected to the socket 8 and a displaying section displays the time of the timer.
申请公布号 JP2692861(B2) 申请公布日期 1997.12.17
申请号 JP19880150603 申请日期 1988.06.17
申请人 发明人
分类号 G04C10/00;G04G19/10;G04G99/00;H03K17/28 主分类号 G04C10/00
代理机构 代理人
主权项
地址