发明名称 Data output circuit, intermediate potential setting circuit, and semiconductor integrated circuit
摘要 An intermediate potential setting circuit includes two MOS transistors having different conductivity types and connected in series between reference power supplies, first and second gate control units, respectively connected to gates of the transistors, for separately ON/OFF-controlling the transistors, a load capacitor connected between the connection node of the transistors and one of the reference power supplies, a control unit, connected between the connection node and the first and second gate control units, for feeding back a potential of the connection node to the first and second gate control units to selectively perform control to turn on the transistors, an external control unit for externally supplying a control signal to the first and second gate control units, and an output terminal, connected to the connection node, for extracting an intermediate potential output as a potential of the load capacitor.
申请公布号 US5698994(A) 申请公布日期 1997.12.16
申请号 US19950507943 申请日期 1995.07.27
申请人 NKK CORPORATION 发明人 TSUJI, KEITARO
分类号 G11C7/10;G11C8/18;H03K19/017;(IPC1-7):H03K19/094 主分类号 G11C7/10
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