| 摘要 |
A clock signal generator inputs a main system clock signal and timing signals to indicate optimum timings for selecting and outputting data, respectively, in an integrated circuit to be accessed which performs based on a specified clock signal with respect to the main clock signal. The clock signal generator outputs clock signals having different duty ratios of the main clock signal according to the timing signals for a precharge operation and a readout operation for the integrated circuit. A precharge type integrated circuit including the clock signal generator outputs data therein correctly according to an address signal and the timing signals from the clock signal generator.
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