发明名称 CPU SYSTEM
摘要 PROBLEM TO BE SOLVED: To continuously operate a system as it is without being affected even when any abnormality occurs on a data bus by judging the normality of the data bus by collating data sent from a memory part through the data bus with data read out of the memory of a collating part. SOLUTION: When reading the contents in a memory 21 of a memory part 20 through a CPU 11, the CPU 11 reads program data while using a data bus A(1) from the memory 21 and writes the contents into a RAM 12. At the same time, the address of a memory 31 is designated to a collating part 30 by the CPU 11 and program data 7 having the same contents as program data 6 in the memory 21 are outputted to a collation circuit 32 and collated with the program data 6, which are inputted through a data bus selection circuit 33, on the data bus A(1) by the collation circuit 32. When the collation at the collation circuit 32 shows coincidence, the collating part 30 judges the data bus A(1) normal but when it shows non-coincidence, the data bus is judged abnormal.
申请公布号 JPH09325920(A) 申请公布日期 1997.12.16
申请号 JP19960165139 申请日期 1996.06.06
申请人 SAITAMA NIPPON DENKI KK 发明人 IWAZAWA KAZUNORI
分类号 G06F11/16;G06F11/00;G06F13/00 主分类号 G06F11/16
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