| 摘要 |
PROBLEM TO BE SOLVED: To omit data processing job and to increase the execution speed of a bit arrangement/read method by arranging higher specific bits at a prescribed number of 1st A/D conversion result storage registers and then arranging other bits at a 2nd A/D conversion result storage register through the MSB(most significant bit) side. SOLUTION: The digital data of d-bit length (8.n<d<8.(n+1)) outputted from an A/D converter 12 are stored in the A/D conversion result storage registers 14 and 16 having 8.n-bit (n: a natural number) width. In this case, higher 8.n bits are arranged at a prescribed number of first registers 14 out of the digital data received from the converter 12. At the same time, other (d-8.n) bits are arraigned at the second register 16 through the MSB side. Therefore, a computer which accesses a data bus 18 of 8.n-bit width can read out the necessary number of higher bits just by having a single access to an A/D conversion result storage register. |
