发明名称 |
Semiconductor memory device having two layers of bit lines arranged crossing with each other |
摘要 |
In a semiconductor memory cell array including word lines, bit lines, and a plurality of memory cells arranged at crossings between the word lines and the bit lines, the bit lines are grouped into odd and even numbered groups. A shift redundancy circuit is arranged between each group of odd or even bit lines and sense amplifier and write circuits for the purpose of shifting a defective memory cell to a redundant memory cell.
|
申请公布号 |
US5699308(A) |
申请公布日期 |
1997.12.16 |
申请号 |
US19960686626 |
申请日期 |
1996.07.24 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
WADA, TOMOHISA;UKITA, MOTOMU |
分类号 |
G11C11/401;G11C7/18;G11C11/407;G11C29/00;H01L21/8242;H01L27/10;H01L27/108;H01L27/11;(IPC1-7):G11C7/00;G11C5/06 |
主分类号 |
G11C11/401 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|