BUS CONTROLLER AND INFORMATION PROCESSOR

摘要

PROBLEM TO BE SOLVED: To avoid the generation of a wasteful cycle for waiting synchronization with respect to an external clock signal. SOLUTION: A bus controller 3 controls access to buses 123 and 124 connected with an external device 21 operating by synchronizing with the external clock signal 100 and an external device 20 operating by not synchronizing with the external device 21. The bus controller 3 detects whether an access request from CPU 2 is an access to the external device 21 or an access to the external device 20. At the time of an access to the external device 21, the controller 3 generates an access control signal in synchronism with an external clock signal 100 and supplies it to the external device 21. On the other hand at the time of an access to the external device 20, the controller 3 generates an access control signal in synchronism with an internal clock signal 101 and supplies it to the external device 20.