发明名称 SDRAM, MEMORY MODULE AND DATA PROCESSING DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a technique which reduces the cost of a memory module provided with a parity function. SOLUTION: In accordance with plural data mask signal terminals DQM 0-DQM3, installed in correspondence with data input/output terminals I/O 0-I/O 3 and the logic of the signals given to individual data mask terminals from outside, a SDRAM(Synchronous Dynamic Random Access Memory) is formed, including input control circuits 700-703 and output control circuits 800-803 which allow to control the data input/output from the corresponding data input/output terminals. Such a SDRAM is used as the one exclusively for parity and other inexpensive SDRAMs having no parity function are applied in plural numbers, thereby reducing the cost of memory modules.
申请公布号 JPH09320258(A) 申请公布日期 1997.12.12
申请号 JP19960133040 申请日期 1996.05.28
申请人 HITACHI LTD 发明人 MONMA ATSUKO;OOISHI TSURATOKI
分类号 G11C11/409;G11C11/401;G11C11/407 主分类号 G11C11/409
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