| 摘要 |
<p>PROBLEM TO BE SOLVED: To extremely reduce possibility of erroneous synchronism acquisition decision because of the noise or fading of a transmission line by cyclically integrating plural bit blocks at the time window control part for integration type synchronism acquisition and performing the synchronism acquisition decision based on the result. SOLUTION: An integration part 12 inputs an envelope detecting output and cyclically integrates the plural bit blocks for the unit of a chip in every bit cycle. An integration type peak detection part 13 inputs the output of the integration part 12 and outputs the peak value of the result cyclically integrating the plural bit blocks and the timing of that peak detection. At the time of synchronism acquisition, a switch 16 connects the output side of an integration type peak phase detection part 15 and the input side of a time window center position memory 17. A peak value memory part 23 outputs a reference peak value, which is stored at the time of synchronism acquisition, to a peak degradation detection part 24. When the output peak value of the detection part 13 is degraded more than a fixed value, the detection part 24 outputs a peak degrade signal, a detection part 25 outputs a peak degradation phase signal and a phase control part 26 lets an N frequency divider 22 shift the phase.</p> |
