| 摘要 |
<p>A novel method and apparatus to cache System Management Mode (SMM) data with other data to improve performance and reduce latency of SMM handler routines. This method and apparatus allows SMM data and non-SMM data to be distinguished in the cache without requiring extra cache bits which can add to the cost of implementation. Since SMM data and non-SMM data can coexist in the cache, there is no need for time consuming cache flush cycles when switching between the two modes (1150). Since SMM data can be cached, performance of SMM routines are improved. This method and apparatus defines the SMRAM address range to be a range of addresses (1110) representable by the tag, but not directly corresponding to installed main memory. When accesses are made to SMRAM addresses, they are redirected to an unused portion of main memory. Protection mechanisms (1150) may be implemented to limit access to these SMRAM addresses when not in SMM.</p> |
