Testing apparatus for semiconductors in integrated circuits

摘要

A test system for semiconductors in integrated circuits conveys the ICs into multi-compartmented test trays (TST) on the loading line (300), into the test chamber (100). After completion of the tests, the devices are conveyed to the load section (400) of the handling system, and into a semiconductor receiver (200). The empty test trays are then returned to the loading section to repeat the process. A sorting system and a fault analyser divides the faulty semiconductors from the good, and sorts them into trays corresponding in number to the compartments of the IC carriers. The number of faulty semiconductors in each tray is totalled. If this total exceeds a predetermined programmed-in value, it may be decided that the IC bearer is faulty.