| 摘要 |
A phase locked loop circuit which follows up the phase of an input signal is provided with a phase comparator (150) which compares the phase of an inputted reference signal with that of the input signal inputted as a comparison object synchronously with a prescribed operation clock. Therefore, first and second detecting sections (154 and 155) and JK flip-flops (162 and 163) output data in accordance with the operation clock, and hence the phase shift between NU and ND data based on the difference between the delay amount of each input data by a loop or feedback constituting part and the phase shift between two tri-state logic outputs are eliminated. Since the phase comparison between the inputted two signals, namely between the reference signal and input signal is performed synchronously with the operation clock, the comparison data obtained as a result of the phase comparison is outputted at prescribed time intervals. Therefore, the malfunction of the phase locked loop circuit is reduced as a whole.
|
