Ein Informationsverarbeitungsgerät mit einer Fehlerprüf- und Korrekturschaltung

摘要

An information processing device according to the present invention includes a logical circuit which outputs a signal (S11;S30) for indicating that an error correction has been conducted on a data, when an error check and correction (ECC) circuit detects and corrects an error of data at the time of reading data from a memory cell array (2;21,22) of an electrically erasable programmable ROM (EEPROM). In the information processing device of the present invention, while the EEPROM outputs the correct data by means of the ECC circuit, it can be known whether there exists an error even in a part of the cells in the EEPROM, so that it is possible to alter an address of a memory cell containing an erroneous bit in the EEPROM or to change the EEPROM itself before malfunction occurs in the information processing device having the EEPROM due to a breakdown of the memory cells in the EEPROM.