PLANERIZING METHOD OF SEMICONDUCTOR DEVICE

摘要

On an inter-metal dielectric layer(3) having a step coverage, a cap layer(4) having a low polishing rate relative to the inter-metal dielectric layer(3) is formed. Then, the cap layer(4) and the inter-metal dielectric layer(3) are polished by CMP(chemical mechanical polishing). The polishing rate of the cap layer(4) is lower than that of the inter-metal dielectric(3). Thereby, it is possible to increase a global flatness of step coverage.