Page-mode memory device with multiple-level memory cells

摘要

A page-mode semiconductor memory device comprises a matrix (1) of memory cells (MC') arranged in rows (R) and columns (C), each row (R) forming a memory page (MP1-MPn) of the memory device and comprising at least one group (MW1,MW2-MW2m-1,MW2m) of memory cells (MC'), memory page selection means (2) for selecting a row (R) of the matrix (1), and a plurality of sensing circuits (3') each one associated to a respective column (C) of the matrix. The memory cells (MC') are multiple-level memory cells which can be programmed in a plurality of c=2<b> (b>1) programming states to store b information bits, and the sensing circuits (3') are serial-dichotomic sensing circuits capable of determining, in a number b of consecutive approximation steps, the b information bits stored in the memory cells (MC'), at each step one of said b information bits being determined, said at least one group (MW1,MW2-MW2m-1,MW2m) of memory cells (MC') of a row (R) forming a number b of memory words of a memory page (MP1-MPn). <IMAGE>